1. Field of the Invention
This invention concerns a ferroelectric memory device which utilizes the polarization of ferroelectric material.
2. Description of Related Art
FIG. 14 is a circuit diagram showing the configuration of ferroelectric memory (FeRAM) devices of the prior art. In FIG. 14, the structure of an ordinary FeRAM memory array is shown. This FeRAM device comprises a plurality of word lines WL0 to WL3, a plurality of plate lines PL0 and PL1, and a plurality of bit lines BL0 to BL3. A memory cell is connected to each of these lines. Further, the FeRAM device comprises a sense amplifier 10. Each of the bit lines BL0 to BL3 is connected to this sense amplifier 10. This sense amplifier 10 operates according to a sense amplifier activation signal SAE.
The memory cell M0 contained in the FeRAM device comprises the selection transistor T0 and ferroelectric capacitor C0; similarly, the memory cell M1 comprises the selection transistor T1 and ferroelectric capacitor C1. In general, NMOS transistors are used as the selection transistors. The main current path (channel) of this selection transistor T0 and the ferroelectric capacitor C0 are connected in series between the bit line BL0 and the plate line PL0, in order from the side of the bit line BL0, and the control electrode (gate electrode) of the selection transistor T0 is connected to the word line WL0. The main current path of the selection transistor T1 and the ferroelectric capacitor C1 are connected in series between the bit line BL1 and the plate line PL0, in order from the side of the bit line BL1, and the control electrode of the selection transistor T1 is connected to the word line WL1.
The FeRAM device further comprises a floating control line EQ0 and transistors T4 and T5 for floating control. The main current paths of each of these transistors T4 and T5 are connected in series between the bit lines BL0 and BL1. The point of connection between these main current paths is connected to a ground terminal GND. Each of the control electrodes of the transistors T4 and T5 is connected to the control line EQ0.
Reading of data from such a FeRAM device is generally performed in conformance with the method described in the publication "Low-Power High-Speed LSI Circuits & Technology", pp. 234-236, published by Realize Inc. FIG. 15 is a timing chart showing the data readout operation in a conventional FeRAM device. Below, this readout operation is explained with reference to FIG. 15. In FIG. 15, the symbol "L" signifies ground potential, and the symbol "H" signifies the power supply voltage (Vcc).
At time t1, the floating control line EQ0 is set to level "L", and the bit lines BL0 and BL1 are put in a floating state. Next, at time t2, a voltage VH is applied to the word lines WL0 and WL1, and the gates of the selection transistors T0 and T1 open. The applied voltage VH is higher than the power supply voltage Vcc by an amount equal to the threshold voltage Vt of the selection transistors.
Next, at time t3, the plate line PL0 is set to "H". Read potentials occur on the bit lines BL0 and BL1, via the ferroelectric capacitors C0 and C1 respectively. The capacitances of the capacitors C0 and C1 differ depending on the polarization direction, and so the read potentials occurring on the bit lines BL0 and BL1 differ according to the respective polarization directions.
Next, at time t4, the sense amplifier activation signal SAE is set to "H", and the sense amplifier 10 is activated. The sense amplifier 10 detects the difference in the read potentials occurring on the bit lines BL0 and BL1, and amplifies the potentials to ground potential and to the power supply potential Vcc respectively. These potentials correspond to a logical "0" and "1" respectively after reading.
FIG. 16 is a graph showing the relation between charge in a ferroelectric capacitor and applied voltage. In the graph, the voltage V applied to the ferroelectric capacitor is plotted along the horizontal axis, and the charge Q on the ferroelectric capacitor is plotted along the vertical axis. On the graph, the curve a represents the change in charge when data "1" is read, that is, the capacitance Cf1 of the ferroelectric capacitor when data "1" is stored. The curve b represents the change in charge when data "0" is read, that is, the capacitance Cf0 of the ferroelectric capacitor when data "0" is stored. The straight line c represents the load line; its gradient is determined by the value of the bit line capacitance Cb. The load line c and the horizontal axis intersect at the power supply voltage Vcc. The difference Vl between the voltage at the point of intersection of the load line c and curve a, and the power supply voltage Vcc, corresponds to the bit line potential when data "1" is read out. The difference V0 between the voltage at the point of intersection of the load line c and curve b, and the power supply voltage Vcc, corresponds to the bit line potential when data "0" is read out. It is necessary that the difference .DELTA.V between these bit line potentials V1 and V0 be equal to or greater than the discrimination sensitivity of the sense amplifier.
However, the hysteresis characteristics of ferroelectric capacitors are greatly affected by device fabrication processes, and characteristic degradation occurs readily. As shown in FIG. 16, the capacitances Cf1 and Cf0 of ferroelectric capacitors which have undergone characteristic degradation are reduced, becoming the capacitance Cf1' indicated by the curve a' and the capacitance Cf0' indicated by the curve b', respectively. As a result, the difference V1' between the voltage at the intersection of the load line c and curve a', and the power supply voltage Vcc, is reduced compared with V1. Further, the difference V0' between the voltage at the intersection of the load line c and curve b', and the power supply voltage Vcc, is reduced compared with V0. In particular, due to the properties of ferroelectric materials, there are large fluctuations in the readout potential V1 during reversal. Hence the difference .DELTA.V' between these bit line potentials V1' and V0' is also reduced compared with the original .DELTA.V. This reduction in .DELTA.V means that there is a reduction in the sense margin (the readout margin), and is a direct cause of read errors.
Hence a ferroelectric memory device having a large readout margin has long been sought.